Conventional non-volatile memory (NVM) cells are routinely used in electronic circuitry, such as electronic consumer devices. Some non-volatile memory cells use “split-gate” designs, where transistors in the memory cells have both a floating gate and a control gate. The floating gate in a transistor is typically located at least partially between the source junction of the transistor and the control gate of the transistor.
Non-volatile memory cells implemented in this manner often suffer from various drawbacks. For example, the source junction often needs to have significant overlap with the floating gate, and the source junction often has to be quite deep in a substrate to tolerate high voltages. This increases the overall size of each transistor and reduces the number of memory cells that can be formed in a given area. Also, the fabrication process is often complicated and requires one or more of the following fabrication features: use of a special injector profile, formation of a very thick oxide layer between the floating and control gates, formation of a buried high-voltage source junction that is not self-aligned to the floating gate, and formation of thick gate oxides under the floating gate and control gate. Each of these may increase the cost of the memory cells being formed.